1364.1-2002 IEEE Standard for Verilog Register Transfer

Average syntax and semantics for VerilogR HDL-based RTL synthesis are defined during this usual.

Show description

Read or Download 1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis PDF

Best nonfiction_1 books

Nonlinear and non-Gaussian state-space modeling with Monte Carlo simulations

We recommend nonlinear and nonnormal filters in accordance with Monte Carlo simulation strategies. when it comes to programming and computational specifications either filters are extra tractable than different nonlinear filters that use numerical integration, Monte Carlo integration with significance sampling or Gibbs sampling.

Extra info for 1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis

Sample text

13 Strengths of net types Ignored. 14 Gate and net delays Ignored. 1 min:typ:max delays Ignored. 2 trireg net charge decay Ignored. 6 User-defined primitives (UDPs) Not supported. Copyright © 2002 IEEE. All rights reserved. 1 Behavioral model overview Supported. 2 Procedural assignments Supported. 1 Blocking procedural assignments blocking_assignment ::= variable_lvalue = [ delay_or_event_control ] expression delay_control ::= # delay_value | # ( mintypmax_expression ) delay_or_event_control ::= delay_control | event_control | repeat ( expression ) event_control event_control ::= @ event_identifier | @ ( event_expression ) |@* |@(*) event_expression ::= expression | hierarchical_identifier | posedge expression | negedge expression | event_expression or event_expression | event_expression , event_expression variable_lvalue ::= hierarchical_variable_identifier | hierarchical_variable_identifier [ expression ] { [ expression ] } | hierarchical_variable_identifier [ expression ] { [ expression ] } [ range_expression ] | hierarchical_variable_identifier [ range_expression ] | variable_concatenation A variable shall not be assigned using a blocking assignment and a non-blocking assignment in the same module.

1 Operators Supported. See also subclauses that follow. 1 Operators with real operands Not supported. 2 Binary operator precedence Supported. 3 Using integer numbers in expressions Supported. 4 Expression evaluation order Supported. 5 Arithmetic operators The power operator (**) shall be supported only when both operands are constants or if the first operand is 2. 6 Arithmetic expressions with regs and integers Supported. 7 Relational operators Supported. == shall not be supported. 9 Logical operators Supported.

4 Tri0 and tri1 nets Not supported. 5 Supply nets Supported. 36 Copyright © 2002 IEEE. All rights reserved. 6 regs Supported. See Clause 5 on how edge-sensitive and level-sensitive storage devices are inferred. 1 Operators and real numbers Not supported. 2 Conversion Not supported. 9 Arrays Supported. 1 Net arrays Supported. 2 reg and variable arrays Supported. 3 Memories Supported. Copyright © 2002 IEEE. All rights reserved. 2 Local parameters—localparam Supported. 11 Name spaces Supported. 38 Copyright © 2002 IEEE.

Download PDF sample

Rated 4.47 of 5 – based on 24 votes